ADPCM algorithm and its codec principle
ADPCM (AdapTIve DifferenTIal Pulse Code ModulaTIon, adaptive differential pulse code modulation) combines the adaptive characteristics of APCM and the differential characteristics of DPCM system, is a waveform code with better performance. Its core idea is: use adaptive to change the size of the quantization steps, that is, use small quantization steps to encode small differences, use large quantization steps to encode large differences; use past sample values ​​to estimate the next input sample The predicted value of, so that the difference between the actual sample value and the predicted value is always the smallest. The quantized value recorded by ADPCM is not the amplitude of each sampling point, but the difference between the amplitude of that point and the amplitude of the previous sampling point.
ADPCM is a waveform coding technique that uses high correlation between samples and quantization order adaptation to compress data. The ADPCM standard is a code conversion system, which uses ADPCM conversion technology to realize the mutual conversion between the 64kb / s A-law or u-law PCM (pulse code modulation) rate and the 32kb / s rate. The simplified block diagram of ADPCM is shown in Figure 1.
The input signal of the ADPCM codec is G.711 PCM code, the sampling rate is 8kHz, and each code is expressed by 8 bits, so its data rate is 64kb / s. The output code of ADPCM is the output of the "adaptive quantizer". The output is a differential signal represented by 4 bits. Its sampling rate is still 8kHz, and its data rate is 32kb / s, so that 2: 1 is obtained. Data compression.
The overall structure of the circuit
Based on the ADPCM algorithm, the voice codec VLSI chip can be divided into several modules: encoding, decoding, storage, control and clock. The encoding module realizes the data compression function, converts the input PCM signal into ADPCM code; the storage module saves the encoded ADPCM code under the action of the control module; the decoding module realizes the decompression function, converts the ADPCM code to obtain the PCM code; the control module The role is to control the coordination work of other modules; the clock module mainly realizes the frequency division of the original clock signal of the external crystal oscillator to obtain the clock signal actually required by the circuit system.
The overall structure of the circuit is shown in Figure 2, where En_en and En_de are the enable signals for encoding and decoding, respectively, and RST is the reset signal. When WE is "1", RAM write is valid, and when WE is "0", RAM read is valid, and when CS is "1", RAM can be written or read.
(a) ADPCM encoder
(b) ADPCM decoder
Figure 1 ADPCM simplified block diagram
Circuit design process
This article uses the Top-down method for circuit design. The main design process is as follows: First, based on Verilog HDL, AcTIve-HDL is used to perform RTL description and functional simulation of the circuit; the correct program after functional simulation will be synthesized and adapted in the Quartus II development system; the netlist file will be obtained next (.vo) and the anti-standard file (.sdo) with delay information are transferred into ModelSim SE, and the corresponding device library of the selected device is added for timing simulation; after the timing simulation is passed, the "* .sof" obtained by Quartus II "The file is downloaded to the FPGA through the JTAG configuration mode for actual power-down tests, and the" * .pof "file can also be downloaded into the FPGA through the AS configuration mode for actual power-down tests. The top-level program of the circuit system is as follows.
Figure 2 overall circuit diagram
module ADPCM_TOP (PCM_OUT, PCM_IN, RECORD, PLAY, CLK, CLK8K);
parameter ADDR_WIDTH = 14;
parameter PCM_WIDTH = 8;
input [PCM_WIDTH-1: 0] PCM_IN;
wire [PCM_WIDTH-1: 0] PCM_IN;
output [PCM_WIDTH-1: 0] PCM_OUT;
wire [PCM_WIDTH-1: 0] PCM_OUT;
input CLK, RECORD, PLAY;
output CLK8K;
wire [3: 0] code_in, code_out;
wire en_encoder, en_decoder, re_rst, pl_rst, WE, CS, CLK_8K;
wire [ADDR_WIDTH-1: 0] ADDRESS;
assign CLK8K = CLK_8K;
CLOCK_GE U0 (CLK, RECORD, CLK_8K);
encoder_new U1 (PCM_IN, re_rst, en_encoder, CLK_8K, code_in);
RAM U2 (ADDRESS, WE, CS, CLK_8K, code_in, code_out);
decoder_new U3 (pl_rst, CLK_8K, code_out, en_decoder, PCM_OUT);
controllogic U4 (CS, re_rst, pl_rst, en_encoder, en_decoder, WE, ADDRESS, RECORD, PLAY, CLK_8K);
endmodule
Sub-module circuit design and simulation
The entire voice encoding and decoding VLSI chip includes several parts: encoding circuit, decoding circuit, storage circuit, control circuit and clock circuit. The following describes the design of key circuits in detail.
1 Encoding circuit
The encoding circuit realizes the data compression function, converts the input PCM signal into a uniform PCM code, and then differentiates it with the predicted signal. The resulting differential signal undergoes compression coding through the "adaptive quantizer" to obtain the ADPCM code, and the ADPCM code is returned through "Inverse adaptive quantizer" and "adaptive predictor" are used to construct the next predicted signal. The simulation waveform of the coding circuit is shown in Figure 3, where PCM_IN is the encoder input signal (PCM code), and CODE is the output signal (ADPCM code) obtained after coding.
Figure 3 Coding circuit simulation waveform
2 Decoding circuit
The decoding circuit realizes the decompression function, and the ADPCM code is passed through an "inverse adaptive quantizer" to obtain a quantized differential signal. The quantized differential signal is added to the predicted value to obtain a reconstructed signal, which is then converted into a PCM code. The simulation waveform of the decoding circuit is shown in Figure 4, where CODE is the decoder input signal (ADPCM code) and PCM_OUT is the output signal (PCM code) obtained after decoding. Compared with the PCM_IN before encoding and decoding in Figure 3, it can be seen that the decoding error is very small.
3 Other modules
The control circuit controls the coordination of other circuit modules, enables the memory to write signals while encoding, and enables the output data of the encoding circuit to be stored in the memory in time; enables the memory to read signals while decoding, and encoding and decoding cannot be performed simultaneously. The clock circuit mainly realizes dividing the original clock signal of the external crystal oscillator to obtain the clock signal actually required by the circuit system. The natural frequency of the external crystal used in this system is 14.318MHz, and an 8kHz clock can be obtained after frequency division. The storage circuit saves the encoded ADPCM code (32kb / s) under the action of the control circuit. Since only the function of the circuit needs to be verified, only 2s of recording storage space is set, that is, 64kb storage capacity.
Overall circuit simulation
[table] [/ table] After the sub-module circuit simulation is correct, the whole system is simulated, and the waveform shown in FIG. 5 can be obtained. The simulation input signal PCM_IN excitation is generated using Testbench. When the encoding enable signal RECORD is "0", start encoding, when RECORD jumps to "1", the encoding is masked; at this time the decoding enable signal PLAY is "0", start decoding, PLAY jumps to "1" , Decoding is blocked. It can be seen from the figure that the excitation of the input signal PCM_IN before encoding and the response of the output PCM_OUT after decoding are basically consistent. Because the ADPCM algorithm itself is lossy compression, it can be determined that the design of this circuit system is correct and reliable.
FPGA verification and conclusion
This article is based on FPGA to verify the designed circuit. The EP1C6Q240C8 device of the Cyclone series of Altera is selected here, which has a storage capacity of 90kb, 6k logic units, and 2 PLLs. Because the circuit uses a sampling frequency of 8kHz, the encoded ADPCM code is 4 bits, and the recording time is set to 2s, so 64kb storage capacity is required; at the same time, the design requires about 400 logic units. So choose this low-cost FPGA to meet the design requirements, and basically make full use of internal resources. This chip has 240 pins, which can meet the external pin connection, and the price is also easy to accept.
FPGA verification shows that the maximum clock delay of the circuit is 26.903ns and the maximum operating frequency can reach 37.17MHz, which can reproduce the recorded voice well, with high fidelity and good real-time performance. It has high application value in the areas of electronic maps, voice broadcasts of vehicle-mounted information terminals, public security alarm systems, especially portable voice recording devices. At the same time, it also pointed out the direction of the efficient design method of digital voice compression processing.
Figure 4 Coding circuit simulation waveform
Figure 5 System simulation waveform
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