Among them, the high-speed clock (HSE and HSI) provides the main clock to the chip body. The low-speed clock (LSE and LSI) is only provided to the RTC (real-time clock) and the independent watchdog in the chip. The high-speed clock can also be seen in the figure. Can be provided to RTC. The internal clock is generated on the chip's internal RC oscillator and starts to oscillate faster. Therefore, when the chip is powered on, the internal high-speed clock is used by default. The external clock signal is input by an external crystal oscillator, which has great advantages in accuracy and stability. Therefore, after power-on, we configure the software to use an external clock signal instead.
High-speed external clock (HSE): With an external crystal as the clock source, the crystal frequency is in the range of 4 to 16 MHz. We generally use an 8 MHz crystal.
High Speed ​​Internal Clock (HSI): Generated by an internal RC oscillator with a frequency of 8 MHz but not stable.
Low-speed external clock (LSE): External crystal oscillator as the clock source, mainly provided to the real-time clock module, so generally use 32.768KHz.
Low-speed internal clock (LSI): Generated by an internal RC oscillator, which is also mainly supplied to the real-time clock module, at a frequency of approximately 40 kHz.
OSC_OUT and OSC_IN start, the two pins are connected to the external crystal oscillator 8MHz, the first divider PLLXTPRE, encounter switching PLLSRC (PLL entry clock source), we can choose its output, the output is an external high-speed clock (HSE) Or internal high speed clock (HSI). Here choose the output as HSE, then encounter the phase-locked loop PLL, with multiplier effect, where we can enter the multiplier factor PLLMUL, if you want to overclock, you have to do tricks in this register. The clock that passes through the PLL is called PLLCLK. The multiplier factor is set to 9x, that is, after the PLL, our clock changes from the original 8MHz HSE to 72MHz PLLCLK. This is followed by a switch SW. After this switch, the STM32 system clock (SYSCLK) is used. Through this switch, the clock source of SYSCLK can be switched, and it can be selected as HSI, PLLCLK, HSE. We chose the PLLCLK clock so the SYSCLK is 72MHz. Before PLLCLK is input to SW, it also flows to the USB prescaler, which outputs the USB peripheral clock (USBCLK). Returning to SYSCLK, the SYSCLK goes through the AHB prescaler and is divided down before being input to other peripherals. If output to the clock called HCLK, FCLK, but also directly output SDIOCLK clock to the SDIO peripheral, memory controller FSMC FSMCCLK clock, and APB1, APB2 prescaler input. The GPIO peripheral is mounted on the APB2 bus. The APB2 clock is the output of the APB2 prescaler, and the APB2 prescaler clock source is the AHB prescaler. Therefore, the APB2 prescaler is set to do not divide the frequency, then we can get GPIO peripheral clock is also equal to HCLK, 72MHz.
SYSCLK: system clock, clock source for most STM32 devices. Mainly by the AHB prescaler assigned to various components.
HCLK: It is obtained by direct output of AHB prescaler. It is the clock signal of high-speed bus AHB and is provided to memory, DMA and cortex cores. It is the clock running by cortex core. The cpu clock is this signal, and its size and STM32 operation. Speed, data access speed is closely related.
FCLK: Also obtained from the output of the AHB prescaler, is the "free running clock" of the core. "Freedom" is that it does not come from the clock HCLK, so FCLK will continue to run when the HCLK clock is stopped. Its existence can guarantee that when the processor sleeps, it can also sample and interrupt and track the sleep event. It synchronizes with the HCLK.
PCLK1: Peripheral clock, which is derived from the APB1 prescaler output. The maximum frequency is 36MHz. It is provided for peripherals mounted on the APB1 bus. Peripherals on the APB1 bus are as follows:
RCC_APB1Periph_TIM2 TIM2 clock
RCC_APB1Periph_TIM3 TIM3 clock
RCC_APB1Periph_TIM4 TIM4 clock
RCC_APB1Periph_WWDG WWDG Clock
RCC_APB1Periph_SPI2 SPI2 Clock
RCC_APB1Periph_USART2 USART2 clock
RCC_APB1Periph_USART3 USART3 clock
RCC_APB1Periph_I2C1 I2C1 clock
RCC_APB1Periph_I2C2 I2C2 clock
RCC_APB1Periph_USB USB Clock
RCC_APB1Periph_CAN CAN Clock
RCC_APB1Periph_BKP BKP clock
RCC_APB1Periph_PWR PWR clock
RCC_APB1Periph_ALL All APB1 peripheral clocks
PCLK2: Peripheral clock, which is obtained from the APB2 prescaler output. The maximum frequency is 72MHz. It is provided for peripherals mounted on the APB2 bus. Peripherals on the APB2 bus are as follows:
The RCC_APB2Periph_AFIO function multiplexes the IO clock
RCC_APB2Periph_GPIOA GPIOA Clock
RCC_APB2Periph_GPIOB GPIOB Clock
RCC_APB2Periph_GPIOC GPIOC clock
RCC_APB2Periph_GPIOD GPIOD Clock
RCC_APB2Periph_GPIOE GPIOE clock
RCC_APB2Periph_ADC1 ADC1 Clock
RCC_APB2Periph_ADC2 ADC2 Clock
RCC_APB2Periph_TIM1 TIM1 clock
RCC_APB2Periph_SPI1 SPI1 clock
RCC_APB2Periph_USART1 USART1 Clock
RCC_APB2Periph_ALL All APB2 peripheral clocks
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