The STM32 family is a 32-bit microcontroller from ST's ARM Cortex-M3 core specifically designed for embedded applications requiring high performance, low cost, and low power. According to the core architecture, it is divided into different products: STM32F series: STM32F103 enhanced series, STM32F101 basic series, STM32F105, STM32F107 interconnected series enhanced series clock frequency reaches 72MHz, which is the highest performance product of its kind; basic clock frequency At 36MHz, the price of 16-bit products has been greatly improved compared to 16-bit products, making it the best choice for 32-bit users.
The input capture mode can be used to measure the pulse width or the measurement frequency. STM32 timers, in addition to TIM6 and TIM7, have other input capture functions. The STM32 input capture, simply by detecting the edge signal on TIMx_CHx, stores the current timer value (TIMx_CNT) in the corresponding channel capture when the edge signal transitions (such as rising/falling edges). /Compare registration (TIMx_CCRx) inside, complete a capture. It is also possible to configure whether interrupt/DMA is triggered during capture.
For example, we use TIM5_CH1 to capture the high-level pulse width, that is, first set the input capture to the rising edge detection, and record the value of TIM5_CNT when the rising edge occurs. The capture signal is then configured to capture on the falling edge. When the falling edge comes, the capture occurs and the TIM5_CNT value at this time is recorded. Thus, the difference between TIM5_CNT and TMB5_CNT is the pulse width of the high level, and the counting frequency of TIM5 is known, so that the accurate time of the high pulse width can be calculated.
First TIMx_ARR and TIMx_PSC, these two registers are used to set the auto-reload value and TIMx clock division.
Let's take a look at the capture/compare mode register 1: TIMx_CCMR1. This register is very useful when the input is captured; TIMx_CCMR1 is obviously for the configuration of 2 channels, and the lower 8 bits [7:0] are used to capture/compare the control of channel 1. The upper eight bits [15:8] are used to capture/compare the control of channel 2. Because TIMx also has the CCMR2 register, it can be known that CCMR2 is used to control channel 3 and channel 4 (see the STM32 Reference Manual for details). 290 pages, section 14.4.8).
Here we use TIM5 capture/compare channel 1, we focus on the [7:0] bits of TIMx_CMMR1 (actually the high 8-bit configuration is similar).
Let's take a look at the capture/compare enable register: TIMx_CCER;
Next, let's take a look at the DMA/Interrupt Enable Register: TIMx_DIER. We need to use the interrupt to process the capture data, so we must enable the channel 1 capture compare interrupt, that is, CC1IE is set to 1.
Control register: TIMx_CR1, we only use its lowest bit, which is used to enable the timer;
Finally, take a look at the capture/compare register 1: TIMx_CCR1, which is used to store the value of TIMx_CNT when the capture occurs. We can read the TIMx_CNT value at the time of channel 1 capture from TIMx_CCR1, and capture it twice (once a rising edge) The difference between the one falling edge and the falling edge can be used to calculate the width of the high level pulse.
Enable capture and update interrupts (set the DIER register of the TIM5)
Because we want to capture the pulse width of the high level signal, the first capture is the rising edge, the second capture is the falling edge, and after the rising edge is captured, the capture edge is set to the falling edge, and if the pulse If the width is long, then the timer will overflow and must be processed for overflow, otherwise the result will be inaccurate. These two things, we are all done inside the interrupt, so we must open the capture interrupt and update the interrupt.
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