1 Hardware platform
1.1 ADSP-BF561 processor
Blackfin561 is a high-performance fixed-point DSP video processing chip in the Blackfin series. Its main frequency is up to 750MHz, and its core contains 2 16-bit multipliers MAC, 2 40-bit accumulator ALUs, 4 8-bit video ALUs, and 1 40-bit shifter. The two sets of data address generators (DAGs) in the chip can provide addresses for accessing dual operands from memory at the same time, and can handle 1200M multiply-add operations per second. The chip has dedicated video signal processing instructions and 100KB of on-chip L1 memory (16KB of instruction cache, 16KB of instruction SRAM, 64KB of data Cache / SRAM, 4KB of temporary data SRAM), 128KB of on-chip L2 memory SRAM, and With dynamic power management function. In addition, the Blackfin processor also includes a wealth of peripheral interfaces, including EBIU interfaces (4 128MB SDRAM interfaces, 4 1MB asynchronous memory interfaces), 3 timers / counters, 1 UART, 1 SPI interface, 2 synchronous serial Interface and 1 parallel peripheral interface (support ITU-656 data format), etc. The Blackfin processor fully embodies the algorithm support for media applications (especially video applications).
1.2 Video encoder platform based on ADSP-BF561
The hardware structure of the Blackfin561 video encoder is shown in Figure 1. The hardware platform uses ADI's ADSP-BF561EZ-kitLite evaluation board. This evaluation board includes an ADSP-BF561 processor, 32MBSDRAM and 4MBFlash. The AD-V1836 audio codec in the board can be connected to 4 input / 6 output audio interfaces, while the ADV7183 video decoder and ADV7171 video encoder can be connected to 3 Input / 3 output video interface In addition, the evaluation board also includes a UART interface, a USB debugging interface and a JTAG debugging interface. In Figure 1, the analog video signal input by the camera is converted into a digital signal by the video chip ADV7183A. This signal is compressed from the Blackfin561 PPI1 (parallel external interface) into the Blackfin561 chip, and the compressed code stream is converted from ADSP-ADV7179 BF561's PPI2 output. This system can load programs through Flash, and supports serial port and network transmission. Data such as original images and reference frames during the encoding process can be stored in SDRAM.
2 Main features of H.264 video compression coding algorithm
Video codec standards mainly include two series: one is MPEG series, and the other is H.26X series. Among them, MPEG series standards are formulated by ISO / IEC organization (International Organization for Standardization), and H.26X series standards are formulated by ITU-T (International Telecommunication Union). I-TU-T standards include H.261, H.262, H.263, H.264, etc., mainly used for real-time video communication, such as video conferencing.
The H.264 video compression algorithm uses a block-based hybrid coding method similar to H.263 and MPEG-4. It uses two coding modes: intra-frame coding (Intra) and inter-frame coding (Inter). Compared with previous coding standards, in order to improve coding efficiency, compression ratio and image quality, H.264 uses the following new coding technology:
(1) H.264 divides the video coding system into two layers: video coding layer (VCL, VideoCodingLayer) and network abstraction layer (NAL, NetworkAbstracTIonLayer) according to function. Among them, VCL is used to complete the efficient compression of video sequences, and NAL is used to standardize the format of video data, mainly providing header information to suit the transmission and storage of various media.
(2) Advanced intra prediction, which uses 4 & TImes; 4 prediction for macroblocks with more spatial detail information, and 16 & TImes; 16 prediction mode for flat areas, the former has 9 prediction methods, the latter There are 4 prediction methods.
(3) Inter prediction uses more block division types. The standard defines 7 different macroblock partitions (16 & TImes; 16, 16 × 8, 8 × 16) and sub-macroblock partitions (8 × 8, 8 × 4, 4 × 8, 4 × 4). Due to the use of smaller blocks and adaptive coding, the amount of data for prediction residuals can be reduced, thereby further reducing the code rate.
(4) High-precision motion prediction based on 1/4 pixel accuracy.
(5) Multi-reference frame prediction is possible. When coding between frames, up to 5 different reference frames can be selected.
(6) Integer conversion (DCT / IDCT). For the 4 × 4 integer transform technology of the residual image, fixed-point arithmetic is used to replace the floating-point arithmetic in the conventional DCT transform. In order to reduce the coding time, it is also more suitable for transplantation to the hardware platform.
(7) H.264 / AVC supports two entropy coding methods, namely CAVLC (Context-based Adaptive Variable Length Coding) and CABAC (Context-based Adaptive Arithmetic Coding). Among them, CAVLC has higher error resistance, but the coding efficiency is lower than that of CABAC; while CABAC has high coding efficiency, but requires more calculation and storage capacity.
(8) Adopt new loop filter technology and entropy coding technology.
These new technologies of H.264 make the moving image compression technology a big step forward. It has better compression performance than MPEG-4 and H.263, and can be applied to high performance such as Internet, digital video, DVD and TV broadcasting The field of video compression.
3 Implementation of H.264 video encoding algorithm
The improvement of H.264 in DSP requires the following three steps: C algorithm optimization on the PC, program migration from the PC to the DSP, and code optimization on the DSP platform.
3.1 C algorithm optimization on PC
According to the system requirements, this design selects ITU's Jm8.5 version baseline profile as the standard algorithm software. ITU's reference software JM is designed based on PC, so it can achieve higher coding effect. When porting video codec software to DSP, DSP system resources should be considered. The main factor to be considered is system space (including program space and data space). Therefore, the original C code needs to be evaluated, which requires The ported code has some understanding. Figure 2 shows the algorithm structure of H.264.
After understanding the algorithm structure, you also need to determine the part that requires a large amount of calculation and takes a long time in the implementation of the encoding algorithm. VC6's own profile analysis tool shows that the intra-frame and inter-frame coding parts occupy more than 60% of the overall running time. Among them, ME (MoveEstimation, motion estimation) takes up more of it. Therefore, the focus of porting and optimization should be on the motion estimation part, so the code structure should be adjusted.
Scope of supply
Rating: Up to 200MVA
Voltage:Valve side voltage up to 1000VDC, Grid side voltage up to 220KV
Double star and double bridge
Applications:
The rectifier transformers are mainly used in the electrolysis processes for production of different kind of metals, such as aluminum electrolyzing, magnesium electrolyzing, copper electrolyzing, zinc electrolyzing and other more applications. The largest installed rectifier transformers are always for aluminum electrolysis with some transformer/rectifier combined units in parallel operation to get the required DC current.
Design:
The rectification method is normally known as double star or double bridge. Double star systems use an interphase transformer (IPT) and are usually applied as 6 or 12pulse units where high currents are required with very low nominal voltages. Double bridge system is applied as 6, 12, 24, 48 or 60pulse systems, as required to suit the harmonic mitigation and process stability requirements.
Duty
Electrolysis is normally a continuous process, but with a constant high loading and current harmonics.
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