Cordic algorithm verilog implementation (complex version)

Module cordic (clk,rst_n,ena,phase_in,sin_out,cos_out,eps);

Parameter DATA_WIDTH=8;

Parameter PIPELINE=8;

Input clk;

Input rst_n;

Input ena;

Input [DATA_WIDTH-1:0] phase_in;

Output [DATA_WIDTH-1:0] sin_out;

Output [DATA_WIDTH-1:0] cos_out;

Output [DATA_WIDTH-1:0] eps;

Reg [DATA_WIDTH-1:0] sin_out;

Reg [DATA_WIDTH-1:0] cos_out;

Reg [DATA_WIDTH-1:0] eps;

Reg [DATA_WIDTH-1:0] phase_in_reg;

Reg [DATA_WIDTH-1:0] x0,y0,z0;

Reg [DATA_WIDTH-1:0] x1,y1,z1;

Reg [DATA_WIDTH-1:0] x2,y2,z2;

Reg [DATA_WIDTH-1:0] x3,y3,z3;

Reg [DATA_WIDTH-1:0] x4,y4,z4;

Reg [DATA_WIDTH-1:0] x5,y5,z5;

Reg [DATA_WIDTH-1:0] x6,y6,z6;

Reg [DATA_WIDTH-1:0] x7,y7,z7;

Reg [1:0] quadrant[PIPELINE:0];

Integer i;

//get real quadrant and map to first_n quadrant

Always@(posedge clk or negedge rst_n)

Begin

If(!rst_n)

Phase_in_reg<=8'b0000_0000;

Else

If(ena)

Begin

Case(phase_in[7:6])

2'b00: phase_in_reg<=phase_in;

2'b01: phase_in_reg<=phase_in-8'h40; //-pi/2

2'b10: phase_in_reg<=phase_in-8'h80; //-pi

2'b11: phase_in_reg<=phase_in-8'hc0; //-3pi/2

Default:;

Endcase

End

End

Always@(posedge clk or negedge rst_n)

Begin

If(!rst_n)

Begin

X0<=8'b0000_0000;

Y0<=8'b0000_0000;

Z0<=8'b0000_0000;

End

Else

If(ena)

Begin

X0<=8'h4D; //define aggregate constant Xi=1/P=1/1.6467=0.60725 (Xi=2^7*P+8'h4D)

Y0<=8'h00;

Z0<=phase_in_reg;

End

End

//level 1

Always@(posedge clk or negedge rst_n)

Begin

If(!rst_n)

Begin

X1<=8'b0000_0000;

Y1<=8'b0000_0000;

Z1<=8'b0000_0000;

End

Else

If(ena)

If(z0[7]==1'b0)

Begin

X1<=x0-y0;

Y1<=y0+x0;

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