DigRF is poised to replace the two main forms of data communication between RF and baseband semiconductor devices: analog signaling, and private digital signaling (parallel or serial) for specific designs. The MIPI (Mobile Industry Processor Interface) Alliance is working to replace the various types of I/Q (in-phase/quadrature phase) signaling interfaces with a packet-based public digital serial interface using the DigRF (digital radio frequency) standard. . A MIPI Alliance working group has developed the DigRF specification for 2.5G and 3G handset standards, and it is expected that subsequent versions will increase data traffic supporting the 4G standard.
Using the standard interface of DigRF allows designers to have more flexibility in component selection. For example, a designer might be prepared to purchase a high-priced baseband IC from one vendor (probably one of the most expensive chips in a handset) and purchase RF, power management, and other devices from other vendors. However, DigRF technology also presents challenges when it comes to the extreme flexibility of general-purpose products that can affect your testing strategy.
During the RF reception test, the test engineer's main goal was the same as before DigRF, namely capturing I/Q information, performing a customized digital signal processing algorithm on the obtained data set, and recording the parameterized results to determine if the device was qualified. However, compared to previous generation RFICs, DigRF devices may add significant overhead to production testing. Finding ways to minimize this overhead is a major challenge for engineers when designing automated production test systems.
Understanding the interfaceDigRF 3G defines the minimum number of signals required to implement an interface; a basic phone configuration requires only 6 wires (Figure 1). The RxData/TxData signal conveys I/Q data and a digital representation of control and status messages in a packet protocol.
Figure 1. The basic DigRF phone configuration requires only 6 wires.
Data transmitted in the DigRF signal is encapsulated in a protocol packet or frame. Each frame consists of three parts: sync (sync), header (header), and payload (Figure 2). Each packet starts with the same 16-bit synchronization sequence, and the digital receiver circuit uses it to align the real-time strobe phase for each frame.
The next 8 bits are the header, which defines the role and content of the payload. The header itself consists of three parts: 3 bits represent the size of the payload, 4 bits describe the LCT (Logical Channel Type), and 1 bit represents the CTS (Clear to Send) signal.
Figure 2. The DigRF 3G data frame begins with a 16-bit sync sequence followed by an 8-bit header and I and Q data.
The payload portion of different packets has a size change, resulting in different levels of coding overhead. The LCT defines what is included in the payload and what can be classified as control data or I/Q data. The CTS allows the data stream from the baseband to be controlled by the RF device during RF transmission.
The remaining N bits in the frame contain the actual data to be transmitted. For example, in the non-diversity mode of DigRF 3G, the RxData frame will use the data channel C and the 256-bit payload, containing 8 bits of alternating I data and Q data.
DigRF 3G supports three timing modes for digital transmission, depending on the type of RF information being transmitted (Table 1). The DigRF standard also supports three common input reference clock frequencies (19.0 MHz, 26.0 MHz, and 38.4 MHz); the clock is sent to the baseband via the SysClk signal. Independent of speed mode, the DigRF processor manages the data stream with a local FIFO buffer that produces an unpredictable timing when transmitting frames.
Production test challengeThe key to successful testing with DigRF protocol devices is to find a way to govern the uncertainty state of the RxData packet during RF reception testing. During the RF reception test of DigRF products, multiple levels of uncertainty in the synthesis state of the RxData signal can be observed:
· Phase timing;
· frame timing;
·Frame type;
· Data in the payload.
The 312 Mbps data rate comes from a 1/4 divider of a 1248 MHz master clock (generally generated by the PLL). In a production test system, the clock input to the device should be provided by the RF instrument, taking into account the importance of the phase noise performance that affects the RF front end. The starting phase of this clock source is usually uncontrollable compared to a normal digital subsystem. The input clock phase of the DUT (device under test) is undetermined, and the phase generated by the PLL multiplier/divider is also uncertain. The combination of the two causes the RxData output timing to be unpredictable, including the power-on cycles of the device, and the parallelism of multiple locations. Test the output timing between different devices in the configuration.
A production tester should have the ability to maintain the operation of the digital subsystem while making necessary modifications to the tester hardware and DUT between tests. It enables the tester to maintain strobe timing relative to the DUT output, avoiding gating phase retuning during formal operation, saving test time.
The next important test challenge is to find a way to handle multi-level uncertainty packet transmission performance. As shown in Figure 3, during each RF receive test of the DUT, the tester does not know in which test cycle each packet will be transmitted, what type of packet will be, or whether the type of packet is as expected (eg, RFIC) An active control status message is generated).
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