First, the background of changes in embedded system design methods
The evolution of embedded system design methods is generally driven by the traction of application requirements and the advancement of IT technology.
With the continuous innovation and development of microelectronics technology, the integration and processing level of large-scale integrated circuits continue to increase. The combination of silicon materials and human intelligence has produced a large number of low-cost, high-reliability and high-precision microelectronic structural modules, driving a new technological field and industry development. The device programmable ideas and micro-processing technology developed on this basis can be used to change and implement hardware functions in software. The large number of applications of microprocessors and various programmable large-scale integrated dedicated circuits and semi-custom devices has created a new world of applications, and has been widely influenced and gradually changed the social activities of human production, life and learning.
The performance of the computer hardware platform has been greatly improved, which has enabled many complex algorithms and easy-to-use interfaces to be realized, greatly improving work efficiency and providing a physical basis for the design of complex embedded system aids.
The high-performance EDA integrated development tools (platforms) have been greatly developed, and their automation and intelligence have been continuously improved. They provide different uses and different levels of editing, layout, routing, compilation, synthesis, and simulation for complex embedded system designs. Integrated, easy-to-learn and easy-to-use development integration environment for testing, verification, and device programming.
The development of the hardware description language HDL (Hardware DescrIPTIon Language) provides a working medium for building various hardware models for complex electronic system design. Its descriptive power and abstraction capabilities have brought about major changes in hardware circuits, especially semi-custom large-scale integrated circuit designs. At present, Verilog HDL, which has become IEEE's STD1076 standard VHDL, IEEE STD 1364 standard, and Altera's enterprise standard AHDL, etc., have been used.
Due to the development and standardization of HDL, there have been a number of companies in the world that use HDL to design professional IC modules. Its task is to use HDL to describe the function and structure of integrated circuits according to common or special functions, and to form different levels of IP core modules through different levels of verification for chip designers to assemble or integrate.
The IP (Intellectual Property) kernel module is a pre-designed or even verified integrated circuit, device or component with certain deterministic functions. It comes in several different forms. The IP core module has different levels of behavior, structure, and physical design, corresponding to the "soft IP core" that mainly describes the functional behavior, and the "solid IP" that describes the structure. The firmware (firm IP core) and the physical description and process-proven "hard IP core" (hard IP core) three levels. This is equivalent to the design techniques of blanks, semi-finished products and finished products of integrated circuits (devices or components).
Soft IP cores are usually submitted to users with some kind of HDL text. It has been designed for behavioral level optimization and functional verification, but it does not contain any specific physical information. According to this, the user can synthesize the correct gate-level netlist and can carry out subsequent structural design, which has the greatest flexibility and can be easily integrated with other external logic circuits by means of EDA synthesis tools, according to various The semiconductor process is designed to have devices with different properties. The total number of gates of a general IP circuit that can be commercialized is more than 5000 gates. However, if the subsequent design is not appropriate, it may cause the entire result to fail. Soft IP cores are also known as virtual devices.
The hard IP core is based on the physical design of a semiconductor process. It has a fixed topology and a specific process, and has been verified by the process to have guaranteed performance. The form that is provided to the user is a circuit physical structure mask layout and a full set of process files, which is a complete set of technologies that can be used.
The design depth of the solid IP core is between the soft IP core and the hard IP core. In addition to completing all the design of the hard IP core, it also completes the design steps of gate level synthesis and timing simulation. It is generally submitted to the user in the form of a gate-level netlist.
Manufacturers such as TI, Philips and Atmel are authorized by Intel to develop their own MC M5151 compatible MCU with their MCS51 IP core module and their own specialties.
Commonly used IP core modules have different CPUs (32/64-bit CISC/RISC-structured CPU or 8/16-bit microcontroller/microcontroller, such as 8051, etc.), 32/64-bit DSP (such as 320C30), DRAM, SRAM, EEPROM, Flashmemory, A/D, D/A, MPEG/JPEG, USB, PCI, standard interfaces, network elements, compilers, encoder/decoders, and analog device modules. The rich IP core module library provides a basic guarantee for the rapid design of ASICs and monolithic systems and the rapid occupation of the market.
Advances in software technology, especially the introduction of the embedded real-time operating system EOS (Embedded OperaTIon System), provide an underlying support and a highly efficient development platform for the development of complex embedded system applications. EOS is a powerful, widely used real-time multitasking system software. It generally has various system resource management functions that the operating system has, and the user can call the function form through the application program interface API to implement various resource management. User programs can be developed and run on the basis of EOS. Compared with the OS in the general-purpose system machine, it mainly has the characteristics of short and fine system kernel, low overhead, strong real-time performance and high reliability. The well-established EOS also provides drivers for a variety of devices. In order to adapt to network applications and Internet applications. TCP/IP protocol support is also available. The current popular EOS includes 3Com's Palm OS, Microsoft's Windows CE and Windows NT Embedded 4.0, Tokyo University's Tron and various open source embedded Linux, and the well-developed Keith Group's Hopen OS and HBOS of Zhejiang University.
MPO/MTP Cassette Module possess optical fiber branching patch cords inside to split the 12-core MPO / MTP connector into simplex or duplex LC connector.
Simplex or duplex connectors are placed in front of the modules, and one or two MPO/ MTP connectors are placed at the back of the modules.
The branching patch cord connect the front LC and the near MPO/MTP connectors. This type of modules can be easily installed in 1U and 4U Chassis.Mpo Cassette Module,Cassette Module For 1U Patch Panel,Mpo-Lc Cassette Module,Mpo Cassette Moudle 24F
ShenZhen JunJin Technology Co.,Ltd , https://www.jjtcl.com