At present, almost 99% of PCB boards require the use of vias. There are many types of vias, including signal holes, power holes, heat dissipation vents, mechanical holes, locating holes, and so on. For hardware engineers, it is very important, especially the signal hole is difficult to design.
The reason why the signal hole is difficult to design is that it contains many factors, such as the aperture, the hole plate, the anti-pad, the length of the stub, etc., which will affect the impedance of the via, and the impedance mismatch is the source of many signal integrity problems. As shown below, the difference in impedance is very large due to the different sizes of vias.
This offline seminar will show you how to model, simulate and design vias. The event will also teach you how to calculate the impedance of the transmission line and the effects of vias and transmission lines on signal integrity. The specific event schedule is as follows:
time and location
Time: December 14, 2017
Venue: Keysight Beijing Office
Address: 2nd Floor Training Class of Keysight Technology, No. 3 Wangjing North Road, Chaoyang District, Beijing
Event schedule
| 08:30 - 09:30 | Sign in |
| 09:30 - 09:45 | Keysight EEsof EDA department profile |
| 09:45 - 10:00 | Signal Integrity Simulation Process Overview |
| 10:00 - 11:00 | Through Hole Design Tool Introduction |
| 11:00 - 12:00 | CILD operation flow |
| 12:00 - 13:30 | lunch |
| 13:00 - 14:00 | Complete signal integrity simulation using via design tools and CILD |
| 14:00 - 16:00 | Practice and answering questions |
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